1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device including multiple insulating films alternately stacked with multiple electrode films and a method for manufacturing the same.
2. Background Art
Nonvolatile semiconductor memory devices of flash memory and the like conventionally are fabricated by two-dimensionally integrating memory cells on a surface of a silicon substrate. In such a semiconductor memory device, it is necessary to increase the integration of memory cells to reduce the cost per bit and increase the storage capacity. However, such high integration in recent years has become difficult in regard to both cost and technology.
Many ideas for three-dimensionally integrated elements are proposed as a technique to breakthrough the limitations of increasing the integration. Even for a constant minimum patterning dimension, the capacity can be increased not only in the plane but also by stacking elements in the perpendicular direction. However, three-dimensional devices generally require several lithography processes for each layer. Therefore, the increase of costs accompanying the increase of lithography processes unfortunately cancels the cost reductions gained by surface area reductions of the silicon substrate; and it is difficult to reduce costs even using three dimensions.
In consideration of such problems, the inventors have proposed a collectively patterned three-dimensional stacked memory (for example, refer to JP-A 2007-266143 (Kokai)). In such technique, a stacked body is formed on a silicon substrate by alternately stacking electrode films and insulating films and subsequently making through-holes in the stacked body by collective patterning. A charge storage layer is formed on a side face of each through-hole, and silicon is buried in an interior of the through-hole to form a silicon pillar. A memory cell is thereby formed at an intersection between each electrode film and the silicon pillar.
In such a collectively patterned three-dimensional stacked memory, a charge can be removed from and put into the charge storage layer from the silicon pillar to record information by controlling electric potential of each electrode film and each silicon pillar. According to such technique, the chip surface area per bit and the cost can be reduced by stacking multiple electrode films on the silicon substrate. Moreover, the three-dimensional stacked memory can be fabricated by collectively patterning the stacked body. Therefore, the number of lithography processes does not increase, and the cost can be prevented from increasing even in the case where the number of stacks increases.
However, it is difficult to collectively make the through-holes in such a collectively patterned three-dimensional stacked memory in the case where the number of stacks increases. It is therefore necessary to make the through-holes by multiple processes. In such a case where the through-hole formed previously is shifted from the through-hole formed thereafter, the cross-sectional area of a connecting portion between the through-holes is undesirably small and increased resistance or opens unfortunately occur in the silicon pillar.